The preparation of printed circuit boards by electroless plating procedures is known, such as those disclosed in "Printed Circuits Handbook", Second Edition, edited by C. F. Coombs, Jr., published by McGraw-Hill Book Co., New York, NY, 1979, Chapter 7; in "Printed Circuit Boards for Microelectronics", Second Edition, by J. A. Scarlett, published by Electrochemical Publications, Ltd., Ayr, Scotland, 1980, Chapter 4 and in "The Multilayer Printed Circuit Board Handbook", edited by J. A. Scarlett, published by Electrochemical Publications, Ltd., Ayr, Scotland, 1985, Chapter 12.
Using electroless plating procedures, various techniques are known to enhance adhesion between substrate and plated metal and to define circuit lines, vias and pads.
Enhancing adhesion by plating onto surfaces roughened mechanically, chemically or by other means is common. In one method, disclosed in U.S. Pat. No. 4,110,147, microscopic pores are replicated in the surface of a thermoset plastic substrate by laminating it to microporous anodized aluminum. The aluminum is removed chemically prior to catalyzing and plating. The method is thus limited to thermoset substrates and requires the added expense and effort of anodizing, laminating and removing the aluminum foil.
In another method, disclosed in U.S. Pat. No. 3,330,695, hard, sharp edged, inert, inorganic dielectric powders, such as aluminum oxide or quartz, are embedded at elevated temperature into a polymeric layer and produce a rough surface from the many interstices present. There is no suggestion that particle microporosity is important or that the particles applied are capable of accepting electrolessly deposited metal; only vacuum sputtering or spraying molten metal is taught. Because of the high temperatures involved, applicability of the method to a wide variety of plastic substrates is uncertain.
A chemical method for roughening a plastic substrate to improve adhesion for electroless plating is the well known "swell and etch" technique. The substrate is treated with a solvent or solvent mixture that will swell, but not dissolve the material. In the swollen condition, the panel is chemically etched with oxidizing reagents such as hot chromic-sulfuric acid to create pits on the surface. The surface-roughened substrate is then screen printed or photoimaged with a resist by known procedures, sensitized and/or catalyzed and electrolessly plated. Alternatively, the resist can be applied after the catalyzing step. With this approach, the degree of plated metal adhesion can be limited depending on the effectiveness of the roughening step, which must be tailored to each different substrate material. The swell and etch technique uses solvents that are volatile and require special procedures and equipment for controlling fumes during application and drying. The hot oxidizing solution is corrosive and hazardous. Further, during the sensitization and catalysis steps, any resist used to define the circuit pattern can pick up catalyst on its surface which lead to unwanted extraneous plating, form nodules or even short circuits and will thus limit the circuit line resolution that can be reliably achieved. If, on the other hand, the entire substrate surface is catalyzed before applying the circuit-defining resist, then the resist must by stripped and the underlying catalytic agents thoroughly removed to prevent the possibility of electrical breakdown when high density circuits are made by this method.
Special cationic copolymers for promoting attachment of negatively charged catalyst species are recommended for treating substrates prior to catalysis in U.S. Pat. No. 4,478,883. While effective for the particular catalytic species specified, it is uncertain how many other catalytic types would be usable.
Another technique for surface roughening prior to circuit pattern formation is suggested in U.S. Pat. Nos. 3,625,758 and 3,546,011. The dielectric substrate contains uniformly dispersed materials, organic or inorganic, which are attacked by oxidizing or caustic reagents and preferentially etched out from the substrate to form the rough surface needed for plating. The U.S. Pat. No. 4,152,477, a butadiene-based rubber adhesive is etched away from hardened phenolic resin microcapsules dispersed in the rubber to provide increased surface area from the presence of the high number of small particles exposed. A characteristic of all these etch-out approaches is that the substrate or adhesive is limited to a narrow range of fillers or matrix materials, thus limiting applicability to a narrow range of substrates, or compromising other properties needed by high performance circuits.
In another approach, e.g., in U.S. Pat. Nos. 3,259,559 and 4,287,253, particulate materials suitable for catalyzing electroless deposition are uniformly dispersed in a polymeric matrix and molded into a dielectric substrate containing uniformly dispersed catalytic sites. Alternatively, such a mixture of polymer and catalyst can be applied as a separate adhesive layer to a dielectric substrate. A resist may be applied to define the circuit before plating. In this method, ionic or metallic species are left permanently on the substrate next to the plated circuit lines. This is unsatisfactory for high density circuits which need better and better dielectric materials for high speed microelectronic applications to prevent electrical breakdown. Also, unless very high catalyst loading is used, the available catalytic sites cover a relatively low fraction of the surface area. This leads to fewer bonding sites per unit area which restricts the adhesive strength obtained by the plated circuit.
In still another method, such as described in U.S. Pat. Nos. 3,391,455 and 3,506,482, the dielectric substrate is imagewise screen printed with an adhesive composition. The resulting adhesive circuit image is rendered catalytic by toning with copper powder. Because image formation is based on screen printing, plated line resolution is inherently low, the resulting circuits have unstraight sidewalls and are thus primarily suitable for lower quality uses or in applications that require only thin conductor layers.
Printed circuits can also be prepared by applying powdered material such as particulate metals onto surfaces having imagewise tacky and nontacky areas. Representative methods are disclosed in U.S. Pat. Nos. 4,054,479, 4,054,483 and 4,454,168. After the particulate metal is applied and unwanted particles are removed, the circuits are formed by one of several additive techniques including electroless plating. Without a separate resist to define circuit line sidewalls, the best applications for this approach are also thin copper layers or low density circuitry.
Methods for imaging without use of resists are known. U.S. Pat. No. 3,822,128 is directed to electroless plating of conductive metal onto a microporous anodized aluminum surface which has been made imagewise catalytic by photoforming metallic silver in the anodized layer. In Japanese Patent Application Publication No. 55-48,472, a conductive circuit is prepared on a dielectric substrate by applying titanium dioxide powder to an adhesive layer previously coated on the substrate, creating a latent image on the titanium dioxide layer by imagewise ultraviolet exposure to a circuit pattern, forming metallic silver plating catalyst on the exposed titanium dioxide particles by treatment with silver nitrate solution, electrolessly plating copper on the catalyzed areas and then curing the adhesive. These approaches suffer from the obvious restriction of being limited to specific materials, an anodized aluminum substrate or titanium dioxide layer. In addition, without the presence of a resist to contain plating, circuit applications would be primarily the lower quality, low definition applications.
In addition, U.S. Pat. No. 4,567,062 describes a process for preparing multilayer printed circuits comprising laminating to a substrate bearing a circuit pattern two photopolymerizable layers that differ in surface and bulk photoresponse; exposing the laminate to actinic radiation through a circuit image related to the circuit pattern on the substrate; embedding finely divided metal or plating catalyst on the tacky image areas; exposing the toned laminate through an image of at least one overlying segment of the conductive circuit pattern; removing unexposed photopolymer from the two layers to form vias; embedding finely divided metal or catalyst to the sidewalls of the vias and plating to form an interconnected conductive circuit. No teaching of embedding microporous particles receptive to catalytic agents is given in this reference, metals such as copper are preferred. The second exposure, whereby vias are formed through the toned circuit image, thus requires up to 10-20.times. the exposure time of the first imaging step. Resolution in the second and any subsequent circuit layers formed by the method of this patent is also limited due to light scattering by the embedded metal particles.
Photosensitive elements with particles embedded in their surfaces are known. In U.S. Pat. No. 4,229,518 there is disclosed an element with (1) a support, (2) at least one toned image-bearing photohardenable layer, (3) a photohardenable protective layer having on its surface finely divided particulate material such as diatomaceous silica. The toning of layer (2) can be carried out with electrically conductive materials. The powder on the surface gives the element a matte finish and renders it nontacky and suitable for handling. U.S. Pat. No. 4,292,389 describes a process where fine particles, to provide a matte surface and good vacuum drawdown, are fused to the surface of a photosensitive printing plate by spraying organic polymeric powders onto the heated plate surface then squeezing them into the photosensitive layer with nip rolls. The particles have a lower softening temperature than the photosensitive coating. U.S. Pat. No. 4,501,810 is directed to a diazo-sensitized lithographic printing plate having on its surface a developer permeable layer of discrete resin particles formed by coating the diazo layer with a resin emulsion, e.g., polystyrene, which is not film forming at room temperature. On exposure, the diazo layer becomes insoluble and adherent to the resin particles. On development, the particles remain on the surface in exposed areas. The plate is finally heat treated to coalesce the resin particles which strengthens and reinforces the image thereby giving longer press life. In these three patents, particles are present only to provide matte appearance or improve handling properties such as nontackiness, toughness or rapid vacuum drawdown. Nothing is disclosed regarding the importance of particle porosity, catalyst receptivity or suitability for electroless plating.
It is an object of this invention to provide a process for making multilayer printed circuit boards, using the electroless plating technique, that results in excellent adhesion and is readily adaptable to achieve high adhesion on a wide variety of substrates--organic, ceramic or metal. It is a particular object to provide a process that is suitable for developing good adhesion on high performance circuit board substrates such as those having low dielectric constant or other desirable properties such as strength, flexibility, or resistance to high temperatures, chemical or environmental attack. It is also an object to achieve high adhesion on such substrates but not require special additives or fillers in the substrate composition that could compromise electrical, physical, thermal or chemical resistance properties of the finished circuit.
It is another object of the invention to provide a process suitable for the highest multilayer circuit line and via definition, for example, circuit lines 0.001 to 0.002 inch (25.4 to 50.8 microns) wide, 0.001 to 0.002 inches (25.4 to 50.8 microns) high with straight sidewalls. These demanding requirements are important in high performance circuits to prevent impedance difficulties that might otherwise ensue.
It is still another object of this invention to provide a process that leaves no trace of metallic or ionic residues on the substrate to cause low resistivity between the conductor lines, thus making the process suitable for producing fine line, high performance multilayer circuitry not subject to electrical breakdown, particularly at high voltages or high temperature and humidity conditions.
Finally, it is an object of the invention to provide a method for making circuits that are ideal for use in producing multilayer circuit boards using existing lamination techniques because their smooth circuit surfaces require only thin adhesive layers between individual boards and minimum pressure in the lamination stage.